[IA64] Mask out reserved bits to avoid Reserved Register/Field faults.

Signed-off-by: Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>

diff --git a/xen/arch/ia64/xen/vcpu.c b/xen/arch/ia64/xen/vcpu.c
index 119fb54b201903f4e28b0b99400bee11d4fa82ab..6c3861a3a9891455020eca3affc231d8c5bdf837 100644 (file)
--- a/xen/arch/ia64/xen/vcpu.c
+++ b/xen/arch/ia64/xen/vcpu.c
@@ -2162,6 +2162,7 @@ vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, u64 vaddr, u64 pte,
        BUG_ON(logps > PAGE_SHIFT);
        vcpu_tlb_track_insert_or_dirty(vcpu, vaddr, entry);
        psr = ia64_clear_ic();
+       pte &= ~(_PAGE_RV2 | _PAGE_RV1);        // Mask out the reserved bits.
        ia64_itc(IorD, vaddr, pte, ps); // FIXME: look for bigger mappings
        ia64_set_psr(psr);
        // ia64_srlz_i(); // no srls req'd, will rfi later

diff --git a/xen/include/asm-ia64/linux-xen/asm/pgtable.h b/xen/include/asm-ia64/linux-xen/asm/pgtable.h
index 7e93544785a6e36f34ae946786a3fdc576a646ee..0ff678491704e742c590cd40384a486b425c3355 100644 (file)
--- a/xen/include/asm-ia64/linux-xen/asm/pgtable.h
+++ b/xen/include/asm-ia64/linux-xen/asm/pgtable.h
@@ -39,6 +39,11 @@
 #define _PAGE_P                        (1 << _PAGE_P_BIT)      /* page present bit */
 #define _PAGE_MA_WB            (0x0 <<  2)     /* write back memory attribute */
 #ifdef XEN
+#define _PAGE_RV1_BIT          1
+#define _PAGE_RV2_BIT          50
+#define _PAGE_RV1              (__IA64_UL(1) << _PAGE_RV1_BIT) /* reserved bit */
+#define _PAGE_RV2              (__IA64_UL(3) << _PAGE_RV2_BIT) /* reserved bits */
+
 #define _PAGE_MA_ST            (0x1 <<  2)     /* is reserved for software use */
 #endif
 #define _PAGE_MA_UC            (0x4 <<  2)     /* uncacheable memory attribute */